/*
 * Copyright (c) 2021 MediaTek Inc.
 *
 * Use of this source code is governed by a MIT-style
 * license that can be found in the LICENSE file or at
 * https://opensource.org/licenses/MIT
 */

#pragma once

/* field definition */
/* ------------------------------------------------------------- */
/* Config */
#define DISP_REG_CONFIG_MMSYS_INTEN                     (DISPSYS_CONFIG_BASE + 0x0)

/* work around 0_2L and 1_2L change*/
#define DISP_REG_CONFIG_MMSYS_MISC                      (DISPSYS_CONFIG_BASE + 0x0F0)
    #define FLD_OVL0_ULTRA_SEL                           REG_FLD_MSB_LSB(5, 2)
    #define FLD_OVL0_2L_ULTRA_SEL                        REG_FLD_MSB_LSB(9, 6)
    #define FLD_OVL1_2L_ULTRA_SEL                        REG_FLD_MSB_LSB(13, 10)

#define DISP_REG_CONFIG_MMSYS_CG_CON0                   (DISPSYS_CONFIG_BASE + 0x100)
#define DISP_REG_CONFIG_MMSYS_CG_SET0                   (DISPSYS_CONFIG_BASE + 0x104)
#define DISP_REG_CONFIG_MMSYS_CG_CLR0                   (DISPSYS_CONFIG_BASE + 0x108)
    #define FLD_CG0_DISP_UFBC_WDMA0                      REG_FLD(1, 30)
    #define FLD_CG0_DSI0_MM                              REG_FLD(1, 29)
    #define FLD_CG0_DISP_DSC                             REG_FLD(1, 27)
    #define FLD_CG0_DITHER0                              REG_FLD(1, 24)
    #define FLD_CG0_POSTMASK0                            REG_FLD(1, 23)
    #define FLD_CG0_DISP_GAMMA0                          REG_FLD(1, 22)
    #define FLD_CG0_DISP_AAL0                            REG_FLD(1, 21)
    #define FLD_CG0_CCORR0                               REG_FLD(1, 19)
    #define FLD_CG0_COLOR0                               REG_FLD(1, 18)
    #define FLD_CG0_DISP_RSZ0                            REG_FLD(1, 17)
    #define FLD_CG0_DISP_RDMA0                           REG_FLD(1, 9)
    #define FLD_CG0_DISP_WDMA0                           REG_FLD(1, 5)
    #define FLD_CG0_OVL0                                 REG_FLD(1, 1)
    #define FLD_CG0_DISP_MUTEX0                          REG_FLD(1, 0)

#define DISP_REG_CONFIG_MMSYS_CG_CON1                   (DISPSYS_CONFIG_BASE + 0x110)
#define DISP_REG_CONFIG_MMSYS_CG_SET1                   (DISPSYS_CONFIG_BASE + 0x114)
#define DISP_REG_CONFIG_MMSYS_CG_CLR1                   (DISPSYS_CONFIG_BASE + 0x118)
    #define FLD_CG1_SMI_COMMON                           REG_FLD(1, 20)
    #define FLD_CG1_DISP_OVL1_2L                         REG_FLD(1, 12)
    #define FLD_CG1_APB_BUS                              REG_FLD(1, 1)
    #define FLD_CG1_DISP_TDSHP0                          REG_FLD(1, 2)

#define DISP_REG_CONFIG_MMSYS_CG_CON2            (DISPSYS_CONFIG_BASE + 0x1A0)
#define DISP_REG_CONFIG_MMSYS_CG_SET2            (DISPSYS_CONFIG_BASE + 0x1A4)
#define DISP_REG_CONFIG_MMSYS_CG_CLR2            (DISPSYS_CONFIG_BASE + 0x1A8)
    #define FLD_CG2_DSI0                          REG_FLD(1, 0)
    #define FLD_CG1_DISP_URGENT                   REG_FLD(1, 11)

#define DISP_REG_CONFIG_MMSYS_LCM_RST_B                 (DISPSYS_CONFIG_BASE + 0x180)

#define DISP_REG_CONFIG_GCE_EVENT_SEL                   (DISPSYS_CONFIG_BASE + 0x308)

#define DISP_REG_CONFIG_SMI_LARB0_GREQ                  (DISPSYS_CONFIG_BASE + 0x8DC)
#define DISP_REG_CONFIG_SMI_LARB1_GREQ                  (DISPSYS_CONFIG_BASE + 0x8E0)


#define DISP_REG_CONFIG_BYPASS_MUX_SHADOW               (DISPSYS_CONFIG_BASE + 0xF00)
    #define FLD_BYPASS_MUX_SHADOW                REG_FLD(1, 0)

#define DISP_REG_CONFIG_DISP_OVL0_UFOD_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF0C)
#define DISP_REG_CONFIG_DISP_OVL0_PQ_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF10)
#define DISP_REG_CONFIG_DISP_OVL0_2L_UFOD_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF14)
#define DISP_REG_CONFIG_DISP_OVL0_2L_PQ_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF18)
#define DISP_REG_CONFIG_DISP_OVL1_2L_UFOD_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF1C)
#define DISP_REG_CONFIG_DISP_OVL1_2L_PQ_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF20)
#define DISP_REG_CONFIG_DISP_RSZ0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF24)
#define DISP_REG_CONFIG_DISP_MAIN_OVL_DMDP_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF28)
#define DISP_REG_CONFIG_DISP_MAIN_OVL_DISP_WDMA_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF2C)
#define DISP_REG_CONFIG_DISP_MAIN_OVL_DISP_UFBC_WDMA_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF30)
#define DISP_REG_CONFIG_DISP_MAIN_OVL_DISP_PQ0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF34)
#define DISP_REG_CONFIG_DISP_PQ0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF38)
#define DISP_REG_CONFIG_DISP_RDMA0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF3C)
#define DISP_REG_CONFIG_DISP_RDMA0_POS_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF40)
#define DISP_REG_CONFIG_DISP_C3D0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF44)
#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF48)
#define DISP_REG_CONFIG_DISP_MDP_AAL0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF4C)
#define DISP_REG_CONFIG_DISP_CHIST0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF50)
#define DISP_REG_CONFIG_DISP_CHIST1_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF54)
#define DISP_REG_CONFIG_DISP_RDMA1_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF58)
#define DISP_REG_CONFIG_DISP_RDMA1_POS_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF5C)
#define DISP_REG_CONFIG_DISP_MERGE0_L_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF60)
#define DISP_REG_CONFIG_DISP_MERGE0_R_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF64)
#define DISP_REG_CONFIG_DISP_DSC_WRAP0_L_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF68)
#define DISP_REG_CONFIG_DISP_DSC_WRAP0_R_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF6C)
#define DISP_REG_CONFIG_DISP_WDMA0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF70)
#define DISP_REG_CONFIG_DISP_UFBC_WDMA0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF74)
#define DISP_REG_CONFIG_DISP_MAIN0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF78)
#define DISP_REG_CONFIG_DISP_SUB0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF7C)
#define DISP_REG_CONFIG_DISP_WDMA1_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF80)
#define DISP_REG_CONFIG_DISP_DSI0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF84)
#define DISP_REG_CONFIG_DISP_DP_INTF0_SEL_IN \
    (DISPSYS_CONFIG_BASE + 0xF88)
#define DISP_REG_CONFIG_DISP_RSZ0_MAIN_OVL_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xF8C)
#define DISP_REG_CONFIG_DMDP_MAIN_OVL_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xF90)
#define DISP_REG_CONFIG_DISP_OVL0_BG_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xF94)
#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xF98)
#define DISP_REG_CONFIG_DISP_TDSHP0_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xF9C)
#define DISP_REG_CONFIG_DISP_C3D0_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFA0)
#define DISP_REG_CONFIG_DISP_CCORR1_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFA4)
#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFA8)
#define DISP_REG_CONFIG_DISP_PQ0_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFAC)
#define DISP_REG_CONFIG_DISP_TV0_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFB0)
#define DISP_REG_CONFIG_DISP_DLI0_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFB4)
#define DISP_REG_CONFIG_DISP_DLI2_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFB8)
#define DISP_REG_CONFIG_DISP_MAIN0_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFBC)
#define DISP_REG_CONFIG_DISP_SUB0_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFC0)
#define DISP_REG_CONFIG_DISP_SUB0_TX_SOUT_SEL \
    (DISPSYS_CONFIG_BASE + 0xFC4)
#define DISP_REG_CONFIG_DISP_Y2R0_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFC8)
#define DISP_REG_CONFIG_DISP_OVL0_BLEND_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFCC)
#define DISP_REG_CONFIG_DISP_OVL0_2L_BLEND_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFD0)
#define DISP_REG_CONFIG_DISP_OVL1_2L_BLEND_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFD4)
#define DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFD8)
#define DISP_REG_CONFIG_DISP_RDMA0_POS_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFDC)
#define DISP_REG_CONFIG_DISP_POSTMASK0_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFE0)
#define DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFE4)
#define DISP_REG_CONFIG_DISP_SPR0_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFE8)
#define DISP_REG_CONFIG_DISP_OVL0_2L_NWCG_BLEND_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFEC)
#define DISP_REG_CONFIG_DISP_MERGE0_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFF0)
#define DISP_REG_CONFIG_DISP_DSC_WRAP0_MOUT_EN \
    (DISPSYS_CONFIG_BASE + 0xFF4)

#define DISP_REG_CONFIG_MMSYS_DL_VALID0                 (DISPSYS_CONFIG_BASE + 0xE9C)
#define DISP_REG_CONFIG_MMSYS_DL_VALID1                 (DISPSYS_CONFIG_BASE + 0xEA0)
#define DISP_REG_CONFIG_MMSYS_DL_VALID2                 (DISPSYS_CONFIG_BASE + 0xEA4)
#define DISP_REG_CONFIG_MMSYS_DL_VALID3                 (DISPSYS_CONFIG_BASE + 0xE80)
#define DISP_REG_CONFIG_MMSYS_DL_VALID4                 (DISPSYS_CONFIG_BASE + 0xE84)
#define DISP_REG_CONFIG_MMSYS_DL_VALID5                 (DISPSYS_CONFIG_BASE + 0xE88)
#define DISP_REG_CONFIG_MMSYS_DL_READY0                 (DISPSYS_CONFIG_BASE + 0xEA8)
#define DISP_REG_CONFIG_MMSYS_DL_READY1                 (DISPSYS_CONFIG_BASE + 0xEAC)
#define DISP_REG_CONFIG_MMSYS_DL_READY2                 (DISPSYS_CONFIG_BASE + 0xEB0)
#define DISP_REG_CONFIG_MMSYS_DL_READY3                 (DISPSYS_CONFIG_BASE + 0xE70)
#define DISP_REG_CONFIG_MMSYS_DL_READY4                 (DISPSYS_CONFIG_BASE + 0xE74)
#define DISP_REG_CONFIG_MMSYS_DL_READY5                 (DISPSYS_CONFIG_BASE + 0xE78)

#define DISP_REG_CONFIG_MMSYS_OVL_CON                   (DISPSYS_CONFIG_BASE + 0xF08)
    #define FLD_CON_OVL1_2L                              REG_FLD(2, 4)
    #define FLD_CON_OVL0_2L                              REG_FLD(2, 2)
    #define FLD_CON_OVL0                                 REG_FLD(2, 0)

/* SMI_LARB0 */
#define DISP_REG_SMI_LARB0_NON_SEC_CON          (DISPSYS_SMI_LARB0_BASE+0x380)
#define DISP_REG_SMI_LARB0_SEC_CON              (DISPSYS_SMI_LARB0_BASE+0xf80)
/* SMI_LARB1 */
#define DISP_REG_SMI_LARB1_NON_SEC_CON          (DISPSYS_SMI_LARB1_BASE+0x380)
#define DISP_REG_SMI_LARB1_SEC_CON              (DISPSYS_SMI_LARB1_BASE+0xf80)
#define REG_FLD_MMU_EN                           REG_FLD(1, 0)
/* SMI_SUBCOM0 */
#define DISP_REG_SMI_SUBCOM0_L1LEN                      (DISPSYS_SMI_SUBCOM0_BASE+0x100)

/* APMIXED */
#define DISP_REG_APMIXED_PLL_CON0   (DISPSYS_APMIXED_BASE+0x14)
#define FLD_PLL_MIPI_DSI0_26M_CK_EN    REG_FLD_MSB_LSB(17, 16)

/* field definition */
/* ------------------------------------------------------------- */
